Cooper LP800 Podręcznik Użytkownika

MicroSim Corporation20 Fairbanks(714) 770-3022Irvine, California 92618 MicroSim PSpice A/D & Basics+Circuit Analysis SoftwareUser’s Guide

x ContentsDefining Output Strengths . . . . . . . . . . . . . . . . . . . . . . . . . 7-21Configuring the strength scale .

Using Global Parameters and Expressions for Values 3-15To declare a global parameter1Place a PARAM symbol in your schematic.2Double-click the PARAM sy

3-16 Preparing a Schematic for SimulationExpressionsAn expression is a mathematical relationship that you can use to define a numeric or boolean (TRUE

Using Global Parameters and Expressions for Values 3-17NoteThough PSpice A/D accepts expressions of any length, Schematics does not. Value assignments

3-18 Preparing a Schematic for SimulationTable 3-2Functions in Arithmetic ExpressionsThis function... Means this...ABS(x) |x|SQRT(x) x1/2EXP(x) exLOG(

Using Global Parameters and Expressions for Values 3-19*. M(x), P(x), R(x), and IMG(x) apply to Laplace expressions only.SDT(x) time integral of x whi

3-20 Preparing a Schematic for SimulationTable 3-3System VariablesThis variable...Evaluates to this...TEMP Temperature values resulting from a tempera

Defining Power Supplies 3-21Defining Power SuppliesFor the Analog Portion of Your CircuitIf the analog portion of your circuit requires DC power, then

3-22 Preparing a Schematic for SimulationTTL DIGIFPWRECL 10K ECL_10K_PWRECL 100K ECL_100K_PWRFor this logic family... Use this symbol...

Defining Stimuli 3-23Defining StimuliTo simulate your circuit, you need to connect one or more source symbols that describe the input signal that the

3-24 Preparing a Schematic for SimulationTo determine the symbol name for an equivalent current source1In the table of voltage source symbols, replace

Contents xiOverview of DC Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3Setting Up a DC Stimulus . . .

Defining Stimuli 3-25If you want to specify multiple stimulus typesIf you want to run more than one analysis type, including a transient analysis, the

3-26 Preparing a Schematic for SimulationUsing VSRC or ISRC symbolsThe VSRC and ISRC symbols have one attribute for each analysis type: DC, AC, and TR

Defining Stimuli 3-27*. The DIGSTIM, IF_IN and INTERFACE symbols require the Stimulus Editor to define the input signal; these symbols are not availab

3-28 Preparing a Schematic for SimulationThings to Watch ForThis section includes troubleshooting tips for some of the most common reasons why your ci

Things to Watch For 3-29Analog Libraries with Modeled PartsDigital Libraries with Modeled PartsTo find out more about a particular library, refer to t

3-30 Preparing a Schematic for SimulationCheck for this if the part in question is custom-builtAre there blank (or inappropriate) values for the symbo

Things to Watch For 3-31Check for this• Does the relevant model library, stimulus file, or include file appear in the configuration list?• If the file

3-32 Preparing a Schematic for SimulationThe MicroSim libraries include parts that are suitable for both simulation and board layout. These parts may

Things to Watch For 3-33Missing DC Path to GroundIf for selected nets in your circuit you see this message in the PSpice output file,ERROR -- Node nod

Creating and Editing Models4Chapter OverviewThis chapter provides information about creating and editing models for parts that you want to simulate.To

xii ContentsMinimum program setup requirements . . . . . . . . . . . . . . . . 11-2Defining a Time-Based Stimulus . . . . .

4-2 Creating and Editing ModelsBackground informationThese topics present model library concepts and an overview of the tools that you can use to crea

What Are Models? 4-3What Are Models?A model defines the electrical behavior of a part. On your schematic, this correspondence is defined by a symbol’s

4-4 Creating and Editing ModelsExample: * FIRST ORDER RC STAGE.SUBCKT LIN/STG IN OUT AGND + PARAMS: C1VAL=1 C2VAL=1 R1VAL=1 R2VAL=1+ GAIN=1000

How Are Models Organized? 4-5Model Library ConfigurationPSpice A/D searches model libraries for the model names specified by the MODEL attribute value

4-6 Creating and Editing ModelsNested Model LibrariesBesides device model and subcircuit definitions, model libraries can also contain references to o

Tools to Create and Edit Models 4-7Tools to Create and Edit ModelsThere are three tools that you can use to create and edit model definitions. Use the

4-8 Creating and Editing ModelsWays to Create and Edit ModelsThis section is a roadmap to other information in this chapter. Find the task that you wa

Ways to Create and Edit Models 4-9* For a list of device types that the Parts utility supports, see Parts-Supported Device Types on page 4-12. If the

4-10 Creating and Editing ModelsUsing the Parts Utility toEdit ModelsThe Parts utility converts information that you enter from the part manufacturer’

Using the Parts Utility to Edit Models 4-11Ways to Use the Parts UtilityYou can use the Parts utility five ways:• To define a new model, and then auto

Contents xiiiMonte Carlo and Sensitivity/Worst-Case AnalysesChapter 13Chapter Overview . . . . . . . . . . . . . . . . . . . . .

4-12 Creating and Editing ModelsParts-Supported Device TypesTable 4-1 summarizes the device types supported in the Parts utility. *. This is the stand

Using the Parts Utility to Edit Models 4-13Ways To Characterize ModelsFigure 4-2 shows two ways to characterize models using the Parts utility.Creatin

4-14 Creating and Editing ModelsAnalyzing the effect of model parameters on device characteristicsYou can also edit model parameters directly and inve

Using the Parts Utility to Edit Models 4-15To fit the model1For each device characteristic that you want to set up:aIn the Model Spec list, select the

4-16 Creating and Editing ModelsRunning the Parts Utility AloneIf you want to: • model a new part and use the part in any schematic (and automatically

Using the Parts Utility to Edit Models 4-172If not already checked, select Always Create Symbol to enable automatic symbol creation.3In the Save Symbo

4-18 Creating and Editing ModelsRunning the Parts Utility from the Symbol EditorIf you want to: • base a new part on an existing symbol, or• edit the

Using the Parts Utility to Edit Models 4-19The symbol editor searches the model libraries for the model. • If found, the symbol editor opens the model

4-20 Creating and Editing ModelsRunning the Parts Utility from the Schematic EditorIf you want to: • test behavior variations on a part, or• refine a

Using the Parts Utility to Edit Models 4-21Starting the Parts utilityTo start editing an instance model1In the schematic editor, select one symbol on

xiv ContentsDigital SimulationChapter 14Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-22 Creating and Editing ModelsWhat happens if you don’t save the instance modelBefore the schematic editor starts the Parts utility, it does these t

Using the Parts Utility to Edit Models 4-23The Parts Utility TutorialIn this tutorial, you will model a simple diode device as follows:• Create the sc

4-24 Creating and Editing ModelsStarting the Parts utility for the D1 diodeTo start the Parts utility1Click the D1 symbol to select it.2From the Edit

Using the Parts Utility to Edit Models 4-25You can modify each model characteristic listed in the Model Spec list with new values from the data sheets

4-26 Creating and Editing ModelsTo change the Forward Current characteristic1In the Model Spec list, double-click Forward Current.The Edit Model Spec-

Using the Parts Utility to Edit Models 4-27Extracting model parametersTo generate new model parameter values1From the Extract menu, select Parameter.

4-28 Creating and Editing ModelsAdding curves for more than one temperatureBy default, the Parts utility computes device curves at 27°C. For any chara

Using the Model Editor 4-29Completing the model definitionYou can refine the model definition by:• modifying the entered data as described before, or•

4-30 Creating and Editing ModelsChanging Model PropertiesThe model editor window contains an edit area that displays the PSpice commands and netlist e

Using the Model Editor 4-31Editing .SUBCKT definitionsFor definitions implemented as subcircuit netlists using PSpice .SUBCKT syntax, the model editor

Contents xvSetting the Default A/D Interface . . . . . . . . . . . . . . . . . . . . . . 15-6Specifying Digital Power Supplies

4-32 Creating and Editing ModelsStart the model editor.2Create or load a symbol definition.3From the Edit menu, click Attribute.aMake sure that your s

Using the Model Editor 4-33Running the Model Editor from the Schematic EditorIf you want to: • define tolerances on model parameters for statistical a

4-34 Creating and Editing ModelsStarting the model editorTo start editing an instance model1In the schematic editor, select the symbol on your schemat

Using the Model Editor 4-35Example: Editing a Q2N2222 Instance ModelSuppose you have a schematic named my.sch that contains several instances of a Q2N

4-36 Creating and Editing ModelsFigure 4-9 shows how the model definition looks after having made these changes.Figure 4-9Model Editor Showing Q2N2222

Using the Create Subcircuit Command 4-37Using the Create Subcircuit CommandThe Create Subcircuit command in the schematic editor creates a subcircuit

4-38 Creating and Editing Modelsschematic_name.sub as either a model library or include file (see Configuring Model Libraries on page 4-41).7If necess

Reusing Instance Models 4-395In the Model Name text box, type the name of the existing model that you want to use.6Click OK.To change the model refere

4-40 Creating and Editing ModelsReusing Instance Models in the Same SchematicThere are two ways to use the instance model elsewhere in the same schema

Configuring Model Libraries 4-41Configuring Model LibrariesThough model libraries are usually configured for you, there are things that you sometimes

xvi ContentsOther Ways to Run Probe . . . . . . . . . . . . . . . . . . . . . . . . . 17-12Starting Probe during a simulatio

4-42 Creating and Editing Models•Add Library* for global models.

Configuring Model Libraries 4-43How PSpice A/D Uses Model LibrariesPSpice A/D searches libraries for any information it needs to complete the definiti

4-44 Creating and Editing ModelsAdding Model Libraries to the ConfigurationSchematics always adds new libraries above the selected library name in the

Configuring Model Libraries 4-45Changing Local and Global ScopeThere are times when you might need to change the scope of a model library from local t

4-46 Creating and Editing Models2If you have listed multiple .lib commands within a single library (like nom.lib), then edit the library using a text

Configuring Model Libraries 4-47To change the library search path1In the schematic editor, from the Options menu, select Editor Configuration.2In the

Creating Symbols for Models5Chapter OverviewThis chapter provides information about creating symbols for model definitions so you can simulate the par

5-2 Creating Symbols for ModelsBackground informationThese topics provide background on the things you need to know and do to prepare for creating sym

What’s Different About Symbols Used for Simulation? 5-3What’s Different About Symbols Used for Simulation?A symbol used for simulation has these speci

5-4 Creating Symbols for ModelsWays to Create Symbolsfor Models*. For a list of device types that the Parts utility supports, see Parts-Supported Devi

Contents xviiRules for numeric values suffixes . . . . . . . . . . . . . . . . . . 17-56Digital Trace Expressions . . . . .

Preparing Your Models for Symbol Creation 5-5Preparing Your Models for Symbol CreationIf you already have model definitions and want to create symbols

5-6 Creating Symbols for ModelsUsing the Symbol WizardIf:• you want to automatically create symbols for a set of similar model definitions that are sa

Using the Symbol Wizard 5-7How the Symbol Wizard WorksThe symbol wizard operates in four phases: setup, automatic symbol creation, refinement, and glo

5-8 Creating Symbols for ModelsPhase 4, Global library configurationWhen you click Finish, the wizard saves the symbols to the symbol library you name

Creating AKO Symbols 5-9NoteAn AKO symbol can only reference base symbols contained in its own library.How to Create AKO SymbolsAKO symbol creation is

5-10 Creating Symbols for Models3Save the base symbol to a new library:aFrom the File menu, select Save As.bType the name of the new library without t

Using the Parts Utility to Create Symbols 5-11Completing the Configuration of Your PartThe only thing left to do is to make sure PSpice A/D knows wher

5-12 Creating Symbols for ModelsStarting the Parts UtilityTo start the Parts utility alone1From the MicroSim program folder, select Parts.2From the Fi

Basing New Symbols On a Custom Set of Symbols 5-13Basing New Symbols On a Custom Set of SymbolsIf you are using the symbol wizard or the Parts utility

5-14 Creating Symbols for Models2For each custom symbol, set its MODEL attribute to `M where ` is a back-single quote or grave symbol.This tells the P

xviii ContentsSetting Initial StateAppendix AAppendix Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Editing Symbol Graphics 5-15Editing Symbol GraphicsIf you created symbols using the symbol wizard or the Parts utility, and you want to make further c

5-16 Creating Symbols for ModelsDefining Important Symbol ElementsOriginThe origin, denoted by a small box with a dashed outline, is the center point

Editing Symbol Graphics 5-17Grid spacing for graphicsThe grid, denoted by evenly spaced grid points, regulates the sizing and positioning of graphic o

5-18 Creating Symbols for ModelsDefining Symbol Attributes Needed for SimulationIf you created your symbols using any of the methods discussed in this

Defining Symbol Attributes Needed for Simulation 5-19MODELThe MODEL attribute defines the name of the model that PSpice A/D must use for simulation. W

5-20 Creating Symbols for ModelsTEMPLATEThe TEMPLATE attribute defines the PSpice A/D syntax for the symbol’s netlist entry. When netlisting, the sche

Defining Symbol Attributes Needed for Simulation 5-21Attribute names in templatesAttribute names are preceded by a special character as follows:[ @ |

5-22 Creating Symbols for ModelsThe ^ character in templatesThe schematic editor replaces the ^ character with the complete hierarchical path to the d

Defining Symbol Attributes Needed for Simulation 5-23TEMPLATE examples Simple resistor (R) templateThe R symbol has:• two pins: 1 and 2• two required

5-24 Creating Symbols for ModelsParameterized subcircuit call (X) templateSuppose you have a subcircuit Z that has:• two pins: a and b• a subcircuit p

FiguresFigure 1-1 Simulation Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8Figure 1-2 Schema

Defining Symbol Attributes Needed for Simulation 5-25Digital stimulus symbols with variable width pins templateFor a digital stimulus device template

5-26 Creating Symbols for ModelsIf the correspondence between pin names and nodes is as follows:then the template would look like this:X^@REFDES %IN+

Defining Symbol Attributes Needed for Simulation 5-27IO_LEVELThe IO_LEVEL attribute defines what level of interface subcircuit model PSpice A/D must u

5-28 Creating Symbols for ModelsMNTYMXDLYThe MNTYMXDLY attribute defines the digital propagation delay level that PSpice A/D must use for a digital pa

Defining Symbol Attributes Needed for Simulation 5-29IPIN attributesIPIN attributes define the net name to which a hidden (invisible) pin is connected

Analog Behavioral Modeling6Chapter OverviewThis chapter describes how to use Analog Behavioral Modeling (ABM) feature provided in PSpice A/D. This cha

6-2 Analog Behavioral ModelingOverview of Analog Behavioral ModelingThe Analog Behavioral Modeling (ABM) feature provided in PSpice A/D allows for fle

The abm.slb Symbol Library File 6-3The abm.slb Symbol Library FileThe symbol file abm.slb contains the ABM components. This file can logically be thou

6-4 Analog Behavioral ModelingPlacing and Specifying ABM PartsABM parts are placed and connected in the same way as other part symbols. Once an ABM sy

Placing and Specifying ABM Parts 6-5resulting netlist. When a match is found, the original fragment is replaced by the fully qualified name of the net

Version 8.0, June, 1997.Copyright 1997, MicroSim Corporation. All rights reserved.Printed in the United States of America.TradeMarksReferenced herein

xx FiguresFigure 4-3 Parts Utility Window with Data for a Bipolar Transistor . . . . . . . . . . . 4-14Figure 4-4 Schematic for a Half-W

6-6 Analog Behavioral ModelingABM Part TemplatesFor most ABM symbols, a single PSpice A/D “E” or “G” device declaration is output to the netlist per s

Control System Parts 6-7Control System PartsControl system parts have single-pin inputs and outputs. The reference for input and output voltages is an

6-8 Analog Behavioral ModelingLaplace TransformLAPLACE Laplace expression NUM, DENOMMath Functions(where ‘x’ is the input)ABS |x|SQRT x1/2PWR |x|EXPEX

Control System Parts 6-9Basic ComponentsThe basic components provide fundamental functions and in many cases, do not require specifying attribute valu

6-10 Analog Behavioral ModelingLimitersThe Limiters can be used to restrict an output to values between a set of specified ranges. These parts are des

Control System Parts 6-11Chebyshev FiltersThe Chebyshev filters allow filtering of the signal based on a set of frequency characteristics. The output

6-12 Analog Behavioral Modelingminimum stop band attenuation is 50 dB. Assuming that the input to the filter is the voltage at net 10 and output is a

Control System Parts 6-13band ripple is 0.1 dB and the minimum stop band attenuation is 50 dB. This will produce a PSpice A/D netlist declaration like

6-14 Analog Behavioral ModelingIntegrator and Differentiator The integrator and differentiator parts are described below.INTEGThe INTEG part implement

Control System Parts 6-15FTABLEThe FTABLE part is described by a table of frequency responses in either the magnitude/phase domain (R_I= ) or complex

Figures xxiFigure 11-3 Example Schematic example.sch . . . . . . . . . . . . . . . . . . . . . . . 11-16Figure 11-4 ECL Compa

6-16 Analog Behavioral ModelingGVALUE parts, Modeling Mathematical or Instantaneous Relationships on page 6-30). The output for each frequency is then

Control System Parts 6-17This part is characterized by the following attributes:ROW1 = 0Hz 0 0ROW2 = 5kHz 0 -5760ROW3 = 6kHz -60 -6912DELAY =R_I =MAGU

6-18 Analog Behavioral ModelingLaplace Transform PartThe LAPLACE part specifies a Laplace transform which is used to determine an output for each inpu

Control System Parts 6-19gain has both a real and an imaginary component. For transient analysis, the output is the convolution of the input waveform

6-20 Analog Behavioral ModelingIf R is small, the characteristic impedance of such a line is Z=((R+j·ω·L)/(j·ω·C))1/2, the delay per unit length is (L

Control System Parts 6-21Math FunctionsThe ABM math function parts are shown in Table 6-2. For each device, the corresponding template is shown, indic

6-22 Analog Behavioral Modelingrequirements. Each of these parts has a set of four expression building block attributes of the form:EXPnwhere n = 1, 2

Control System Parts 6-23In this example of an ABM device, the output voltage is set to 5 volts times the square root of the voltage between net 3 and

6-24 Analog Behavioral ModelingExample 3A device, EPWR, computes the instantaneous power by multiplying the voltage across nets 5 and 4 by the current

Control System Parts 6-25An Instantaneous Device Example: Modeling a TriodeThis section provides an example of using various ABM parts to model a trio

xxii FiguresFigure 16-9 Cumulative Ambiguity Hazard Example 2 . . . . . . . . . . . . . . . . . . 16-8Figure 16-10 Cumulative Am

6-26 Analog Behavioral ModelingEXP1 = V(%IN2,%IN3)+EXP2 = 0.12*V(%IN1,%IN3)This works for the main operating region but does not model the case in whi

Control System Parts 6-27impedance. Capacitances between the grid, cathode, and anode are also needed. The lower part of the schematic in Figure 6-13

6-28 Analog Behavioral ModelingPSpice A/D-Equivalent PartsPSpice A/D-equivalent parts respond to a differential input and have double-ended output. Th

PSpice A/D-Equivalent Parts 6-29voltage output is required, use an E part type. If a current output is necessary, use a G part type.Each E or G part t

6-30 Analog Behavioral ModelingRefer to the online MicroSim PSpice A/D Reference Manual for detailed information. Modeling Mathematical or Instantaneo

PSpice A/D-Equivalent Parts 6-31be either the voltage at a net, such as V(5), or the voltage across two nets, such as V(4,5). Currents must be the cur

6-32 Analog Behavioral ModelingEMULT, GMULT, ESUM, and GSUMThe EMULT and GMULT parts provide output which is based on the product of two input sources

PSpice A/D-Equivalent Parts 6-33where MAXREAL is a PSpice A/D internal constant representing a very large number (on the order of 1e30). In general, t

6-34 Analog Behavioral ModelingTABLE =+ (0, 0) (.02, 2.690E-03) (.04, 4.102E-03) (.06, 4.621E-03)+ (.08, 4.460E-03) (.10, 3.860E-03) (.12, 3.079E-03)

PSpice A/D-Equivalent Parts 6-35Frequency-Domain Device ModelsFrequency-domain models (ELAPLACE, GLAPLACE, EFREQ, and GFREQ) are characterized by outp

TablesTable 1-1 DC Analysis Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3Table 1-2 AC Anal

6-36 Analog Behavioral Modelingfrequency gain times the value of EXPR. The zero frequency gain is the value of XFORM with s = 0. For AC analysis, EXPR

PSpice A/D-Equivalent Parts 6-37gain has both a real and an imaginary component. The gain and phase characteristic is the same as that shown for the e

6-38 Analog Behavioral ModelingThe DELAY attribute increases the group delay of the frequency table by the specified amount. The delay term is particu

PSpice A/D-Equivalent Parts 6-39.001 (-60 dB) for frequencies above 6 kilohertz. The output is a voltage across the output pins.This part is defined b

6-40 Analog Behavioral ModelingCautions and Recommendations for Simulation and AnalysisInstantaneous Device Modeling During AC analysis, nonlinear tra

Cautions and Recommendations for Simulation and Analysis 6-41Frequency-Domain PartsSome caution is in order when moving between frequency and time dom

6-42 Analog Behavioral Modeling(2π) = 159 Hz. At 159 Hz, the response is down to .001 (down by 60 db). Since some transforms do not have such a limit,

Cautions and Recommendations for Simulation and Analysis 6-43A good example of this is the expression {S}, which corresponds to differentiation in the

6-44 Analog Behavioral ModelingTMAX is not specified it is assigned a value, or if it is specified, it may be reduced. For low pass and band pass filt

Cautions and Recommendations for Simulation and Analysis 6-45Trading Off Computer Resources For AccuracyIt should be clear from the foregoing discussi

xxiv TablesTable 14-2 STIMn Part Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17Table 14-3 FI

6-46 Analog Behavioral ModelingBasic Controlled SourcesAs with basic SPICE, PSpice A/D has basic controlled sources derived from the standard SPICE E,

Digital Device Modeling7Chapter OverviewThis chapter provides information about digital modeling, and includes the following sections:Introduction on

7-2 Digital Device ModelingIntroductionThe standard symbol libraries contain a comprehensive set of digital parts in many different technologies. Each

Functional Behavior 7-3Functional BehaviorA digital device model’s functional behavior is defined by one or more interconnected digital primitives. Ty

7-4 Digital Device ModelingTristate GatesBUF3INV3AND3NAND3OR3NOR3XOR3NXOR3BUF3AINV3AAND3ANAND3AOR3ANOR3AXOR3ANXOR3AbufferinverterAND gateNAND gateOR g

Functional Behavior 7-5Programmable Logic ArraysPLANDPLORPLXORPLNANDPLNORPLNXORPLANDCPLORCPLXORCPLNANDCPLNORCPLNXORCAND arrayOR arrayexclusive OR arra

7-6 Digital Device ModelingThe format for digital primitives is similar to that for analog devices. One difference is that most digital primitives req

Functional Behavior 7-7.subckt DotA_STD D A DPWR DGND+ params: DRVL=0 DRVH=0 CAPACITANCE=0N1 A DGND DPWR DIN74 DGTLNET=D IO_STDC1 A DGND {CAPACITANCE+

7-8 Digital Device Modeling<digital power node> <digital ground node>are the nodes used by the interface subcircuits which connect analog

Functional Behavior 7-9IO_LEVELis an optional device parameter which selects one of the four AtoD or DtoA interface subcircuits from the device’s I/O

Before You BeginWelcome to MicroSimWelcome to the MicroSim family of products. Whichever programs you have purchased, we are confident that you will f

7-10 Digital Device Modeling+ MNTYMXDLY={MNTYMXDLY} U3 jkff(1) DPWR DGND+ $D_HI CLRBAR QB_BUF $D_HI $D_HI + QC_BUF $D_NC D_393_2 IO_STD + MNTYMXDLY

Timing Characteristics 7-11Timing CharacteristicsA digital device model’s timing behavior can be defined in one of two ways:• Most primitives have an

7-12 Digital Device Modelingtypical low-to-high propagation delay on a gate is specified as the parameter TPLHTY. The minimum data-to-clock setup time

Timing Characteristics 7-13DIGMNTYSCALEThis option computes the minimum delay when a typical delay is known, using the formula:TPxxMN = DIGMNTYSCALE ⋅

7-14 Digital Device ModelingInstead, when one or more timing constraints are omitted, the simulator uses the following steps to fill in the missing va

Timing Characteristics 7-15When outputs connect to analog devices, the propagation delay is reduced by the switching times specified in the I/O Model.

7-16 Digital Device ModelingThe same device with a short pulse applied produces no output change. However, if TPWRT is assigned a numerical value (1 o

Input/Output Characteristics 7-17Input/Output CharacteristicsA digital device model’s input/output characteristics are defined by the I/O Model that i

7-18 Digital Device ModelingINLD and OUTLDThese are used in the calculation of loading capacitance, which factors into the propagation delay discussed

Input/Output Characteristics 7-19TSWLHn and TSWHLnThese switching times are subtracted from a device’s propagation delay on the outputs which connect

xxvi Before You BeginMicroSim PSpice A/D OverviewMicroSim PSpice A/D can simulate analog-only, mixed analog/digital, and digital-only circuits. PSpice

7-20 Digital Device ModelingAtoD1 (Level 1) name of AtoD interface subcircuitDtoA1 (Level 1) name of DtoA interface subcircuitAtoD2 (Level 2) name of

Input/Output Characteristics 7-21The digital primitives comprising the 74393 part, reference the IO_STD I/O Model in the model libraries as shown:.mod

7-22 Digital Device ModelingConfiguring the strength scaleThe 64 strengths are determined by two configurable options: DIGDRVZ and DIGDRVF. DIGDRVZ de

Input/Output Characteristics 7-23level is at a higher strength than the 1 level (which drives at the Z strength).Drive impedances which are higher tha

7-24 Digital Device Modelingand output leakage currents would be required, as well as low coupling from adjacent signals.The simulator models the stor

Input/Output Characteristics 7-25Creating Your Own Interface Subcircuits forAdditional TechnologiesIf you are creating custom digital parts for a tech

7-26 Digital Device ModelingThe DtoA interface subcircuit format is shown here:.SUBCKT DTOA <name suffix>+ <digital input node> <analog

Input/Output Characteristics 7-27If an instance of the 74393 part is connected to an analog part via node AD_NODE, PSpice A/D generates an interface b

7-28 Digital Device Modeling.subckt DtoA_STD D A DPWR DGND+ params: DRVL=0 DRVH=0 CAPACITANCE=0*N1 A DGND DPWR DIN74 DGTLNET=D IO_STDC1 A DGND {CA

Creating a Digital Model Using the PINDLY and LOGICEXP Primitives 7-29Creating a Digital Model Using the PINDLY and LOGICEXP PrimitivesUnlike the majo

How to Use this Guide xxviiHow to Use this GuideThis guide is designed so you can quickly find the information you need to use PSpice A/D.This guide a

7-30 Digital Device Modelinghold timing from the data sheet. Then the simulator can verify that these conditions are met during the simulation.Digital

Creating a Digital Model Using the PINDLY and LOGICEXP Primitives 7-31name, interface pin list, and parameter list is the LOGICEXP primitive. It conta

7-32 Digital Device Modelingprimitives, see the Digital Devices chapter in the online MicroSim PSpice A/D Reference Manual.IO_STD, shown in the listin

Creating a Digital Model Using the PINDLY and LOGICEXP Primitives 7-33Pin-to-Pin Delay (PINDLY Primitive)The delay and constraint specifications for t

7-34 Digital Device ModelingIn the 74160 model, the boolean expressions are actually reference functions. There are three reference functions availabl

Creating a Digital Model Using the PINDLY and LOGICEXP Primitives 7-35delay in every CASE function. Also note that the expressions must be separated b

7-36 Digital Device ModelingConstraint Checker (CONSTRAINT Primitive)The CONSTRAINT primitive provides a general constraint checking mechanism to the

Creating a Digital Model Using the PINDLY and LOGICEXP Primitives 7-37signal can go inactive before the active clock edge. Again, the _LH and _HL form

7-38 Digital Device ModelingB, C, D) have a setup/hold time of 20 ns in reference to the CLK signal. We are also checking that ENP and ENT have a setu

Creating a Digital Model Using the PINDLY and LOGICEXP Primitives 7-39+ I1C = { (QA & EN & QB) | LOAD }+ I2C = { ~(LOAD & C) }+ JC =

xxviii Before You BeginRelated DocumentationDocumentation for MicroSim products is available in both hard copy and online. To access an online manual

7-40 Digital Device Modeling+ SETUP_HOLD:+ DATA(2) = ENP ENT+ CLOCK LH = CLK+ SETUPTIME = 20NS+ WHEN = { CLRBAR!='0 & (LOADBAR!=&apos

Part ThreeSetting Up and Running AnalysesPart Three describes how to set up and run analyses and provides setup information specific to each analysis

Chapter 13,Monte Carlo and Sensitivity/Worst-Case Analyses, describes how to set up Monte Carlo and sensitivity/worst-case analyses for statistical in

Setting Up Analyses and Starting Simulation8Chapter OverviewThis chapter provides an overview of setting up analyses and starting simulation which app

8-2 Setting Up Analyses and Starting SimulationAnalysis TypesPSpice A/D supports analyses that can simulate analog-only, mixed-signal, and digital-onl

Setting Up Analyses 8-3The Probe waveform analyzer is used to display and graphically analyze the results of PSpice A/D simulations for swept analyses

8-4 Setting Up Analyses and Starting SimulationExecution Order for Standard AnalysesDuring simulation, any analyses that are enabled are performed in

Setting Up Analyses 8-5Output VariablesCertain analyses (such as noise, Monte Carlo, sensitivity/worst-case, DC sensitivity, Fourier, and small-signal

8-6 Setting Up Analyses and Starting SimulationA <pin id> (from line 4) is uniquely distinguished by specifying the full part name (as described

Setting Up Analyses 8-7These building blocks can be used for specifying output variables as shown in Table 8-3 (which summarizes the accepted output v

Related Documentation xxixThe following table provides a brief description of those manuals available online only.Online HelpSelecting Search for Help

8-8 Setting Up Analyses and Starting SimulationTable 8-4Element Definitions for 2-Terminal DevicesDevice Type<out id> or <out device>Devic

Setting Up Analyses 8-9Table 8-5Element Definitions for 3- or 4-Terminal DevicesDevice Type<out id> or <out device>Device Indicator<pin

8-10 Setting Up Analyses and Starting SimulationThe INOISE, ONOISE, DB(INOISE), and DB(ONOISE) output variables are predefined for use with noise (AC

Starting Simulation 8-11Starting SimulationOnce you have used MicroSim Schematics to enter your circuit design and to set up the analyses to be perfor

8-12 Setting Up Analyses and Starting SimulationStarting Simulation Outside of SchematicsTo start PSpice A/D outside of Schematics1Double-click on the

Starting Simulation 8-13Running simulations with multiple circuit filesYou can direct PSpice A/D to simulate multiple circuit files using one of the f

8-14 Setting Up Analyses and Starting SimulationCircuit file names may be fully qualified or contain the wild card characters * and ?.The Simulation S

Starting Simulation 8-15MenusThe menus accessed from the menu bar include items to control the simulator and customize the window display characterist

DC Analyses9Chapter OverviewThis chapter describes how to set up DC analyses and includes the following sections:DC Sweep on page 9-2Bias Point Detail

9-2 DC AnalysesDC SweepMinimum Requirements to Run a DC Sweep AnalysisMinimum circuit design requirementsMinimum program setup requirements• In the An

ContentsBefore You BeginWelcome to MicroSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvMicroSim PSpi

xxx Before You BeginIf You Don’t Have the Standard PSpice A/D PackageIf You Have PSpice A/D Basics+PSpice A/D Basics+ provides the basic functionality

DC Sweep 9-3Overview of DC SweepThe DC sweep analysis causes a DC sweep to be performed on the circuit. DC sweep allows you to sweep a source (voltage

9-4 DC AnalysesTo calculate the DC response of an analog circuit, PSpice A/D removes time from the circuit. This is done by treating all capacitors as

DC Sweep 9-5Setting Up a DC StimulusTo run a DC sweep or small-signal DC transfer analysis, you need to place and connect one or more independent sour

9-6 DC AnalysesNested DC SweepsA second sweep variable can be selected once a primary sweep value has been specified in the DC Sweep dialog box. When

DC Sweep 9-7Curve Families for DC SweepsWhenever a nested DC sweep is performed, the entire curve family is displayed. That is, the nested DC sweep is

9-8 DC AnalysesFigure 9-4Device Curve FamilyFigure 9-5Operating Point Determination for Each Member of the Curve Family

Bias Point Detail 9-9Bias Point DetailMinimum Requirements to Run a Bias Point Detail AnalysisMinimum circuit design requirementsNone.Minimum program

9-10 DC AnalysesWhen the Bias Point Detail analysis is enabled, the following information is reported to the output file:• a list of all analog node v

Small-Signal DC Transfer 9-11Small-Signal DC TransferMinimum Requirements to Run a Small-Signal DC Transfer AnalysisMinimum circuit design requirement

9-12 DC AnalysesOverview of Small-Signal DC TransferThe small-signal DC transfer analysis causes the small-signal transfer function to be calculated b

If You Don’t Have the Standard PSpice A/D Package xxxiNotable PSpice analysis and simulation features DC sweep, AC sweep, transient analysis yes yesno

DC Sensitivity 9-13DC SensitivityMinimum Requirements to Run a DC Sensitivity AnalysisMinimum circuit design requirementsNone.Minimum program setup re

9-14 DC AnalysesOverview of DC SensitivityDC sensitivity analysis calculates and reports the sensitivity of one node voltage to each device parameter

AC Analyses10Chapter OverviewThis chapter describes how to set up AC sweep and noise analyses.AC Sweep Analysis on page 10-2 describes how to set up a

10-2 AC AnalysesAC Sweep AnalysisWhat You Need to Do to Run an AC SweepThe following procedure describes the minimum set of things that you need to do

AC Sweep Analysis 10-3• Digital devices hold the states that PSpice A/D calculated when solving for the bias point.• Because AC sweep analysis is a li

10-4 AC Analyses2Double-click the symbol instance. A dialog box appears listing the attribute settings for the symbol instance.3Depending on the sourc

AC Sweep Analysis 10-5Setting Up an AC AnalysisTo set up the AC analysis1From the Analysis menu, select Setup.2Click AC Sweep.3In the AC Sweep dialog

10-6 AC AnalysesAC Sweep Setup in “example.sch”If you look at the example circuit, example.sch, provided with your MicroSim programs, you’ll find that

AC Sweep Analysis 10-7How PSpice A/D Treats Nonlinear DevicesAn AC Sweep analysis is a linear or small-signal analysis. This means that nonlinear devi

10-8 AC AnalysesUsing a DC sourceConsider the circuit shown here. At the DC bias point, PSpice A/D calculates the partial derivatives which determine

xxxii Before You Begin*. PSpice A/D Basics+ package includes all libraries except IGBTS, SCRs, thyristors, PWMs, magnetic cores, and transmission line

Noise Analysis 10-9Noise AnalysisWhat You Need to Do to Run a Noise AnalysisThe following procedure describes the minimum set of things that you need

10-10 AC AnalysesWhat is Noise Analysis?When running a noise analysis, PSpice A/D calculates and reports the following for each frequency specified fo

Noise Analysis 10-11Setting Up a Noise AnalysisTo set up the noise analysis1From the Analysis menu, select Setup.2Click AC Sweep.3In the AC Sweep dial

10-12 AC AnalysesAnalyzing Noise in ProbeProbe supports these output variable formats, which you can use to view traces for device noise contributions

Noise Analysis 10-13About noise unitsExampleYou can run a noise analysis on the circuit shown in Figure 10-1 on page 10-6. To run a noise analysis on

10-14 AC AnalysesFigure 10-2 shows Probe traces for Q1’s constituent noise sources as well as total nose for the circuit after simulating. Notice that

Transient Analysis11Chapter OverviewThis chapter describes how to set up a transient analysis and includes the following sections:Overview of Transien

11-2 Transient AnalysisOverview of Transient AnalysisMinimum Requirements to Run a Transient AnalysisMinimum circuit design requirementsCircuit should

Defining a Time-Based Stimulus 11-3Defining a Time-Based Stimulus Overview of Stimulus GenerationSymbols that generate input signals for your circuit

11-4 Transient AnalysisTo use any of these source types, you must place the symbol in your schematic and then define its transient behavior. Each attr

If You Don’t Have the Standard PSpice A/D Package xxxiiiIf You Have the Evaluation CD-ROMMicroSim’s evaluation CD-ROM has the following limitations:•

The Stimulus Editor Utility 11-5Figure 11-1Relationship of Stimulus Editor with Schematics and PSpice A/DThe stimulus specification created using the

11-6 Transient AnalysisStimulus FilesThe Stimulus Editor produces a file containing the stimuli with their transient specification. These stimuli are

The Stimulus Editor Utility 11-7Starting the Stimulus EditorThe Stimulus Editor is fully integrated with Schematics and can be run from either the sch

11-8 Transient AnalysisDefining Stimuli1Place stimulus part instances from the symbol set: VSTIM, ISTIM, interface ports (IF_IN and INTERFACE), and DI

The Stimulus Editor Utility 11-98Move the cursor to (200ns, 1) and click the left mouse button. This adds the point. Notice that there is automaticall

11-10 Transient AnalysisbEnter {AMP} for Amplitude. The curly braces are required. They indicate that the expression needs to be evaluated at simulati

The Stimulus Editor Utility 11-112Select Stimulus from the Edit menu. Schematics searches the configured list of global stimulus files. If you are cre

11-12 Transient AnalysisEditing a StimulusTo edit an existing stimulus1Start the Stimulus Editor and select Get from the Stimulus menu.2Double-click t

The Stimulus Editor Utility 11-13Deleting and Removing TracesTo delete a trace from the displayed screen, select the trace name by clicking on its nam

11-14 Transient Analysis4In the schematic editor, configure the Stimulus Editor’s output file into your schematic:aSelect Library and Include Files fr

xxxiv Before You BeginWhat’s NewBias information display on your schematicAfter simulating, you can display bias point information on your schematic s

Transient (Time) Response 11-157To change stimulus references globally for a symbol:aSelect Edit Library from the File menu to start the symbol editor

11-16 Transient AnalysisFigure 11-3Example Schematic example.schThe transient analysis does its own calculation of a bias point to start with, using t

Internal Time Steps in Transient Analyses 11-17Internal Time Steps in Transient AnalysesDuring analog analysis, PSpice A/D maintains an internal time

11-18 Transient AnalysisSwitching Circuits in Transient AnalysesRunning transient analysis on switching circuits can lead to long run times. PSpice A/

Plotting Hysteresis Curves 11-19The QSTD model is defined as:.MODEL QSTD NPN( is=1e-16 bf=50 br=0.1 rb=50 rc=10 tf=.12ns tr=5ns+ cje=.4pF pe=.8 me=.4

11-20 Transient AnalysisFigure 11-6Hysteresis Curve Example: Schmitt TriggerFourier ComponentsFourier analysis is enabled through the transient analys

Fourier Components 11-21In the example Fourier analysis specification shown in Figure 11-2 on page 11-15, the voltage waveform at node OUT2 from the t

Parametric and Temperature Analysis12Chapter OverviewThis chapter describes how to set up parametric and temperature analyses. Parametric and temperat

12-2 Parametric and Temperature AnalysisParametric AnalysisMinimum Requirements to Run a Parametric AnalysisMinimum circuit design requirements• Set u

Parametric Analysis 12-3Overview of Parametric AnalysisParametric analysis performs multiple iterations of a specified standard analysis while varying

What’s New xxxvBSIM3 version 3 MOSFET modelThe BSIM3 version 3 model, which was developed at U.C. Berkeley, is a deep submicron MOSFET model with the

12-4 Parametric and Temperature AnalysisThis series of PSpice A/D runs varies the value of resistor R1 from 0.5 to 1.5 ohms in 0.1 ohm steps. Since th

Parametric Analysis 12-5Using performance analysis to plot overshoot and rise timeAfter performing the PSpice A/D simulation that creates the data fil

12-6 Parametric and Temperature Analysisgenrise( I(L1) )In Figure 12-3, we can see how the rise time decreases as the damping resistance increases for

Parametric Analysis 12-7Now we can use the multiple X axes feature to view the original waveform family for inductor L1 current along with the derived

12-8 Parametric and Temperature AnalysisExample: Frequency Response vs. Arbitrary ParameterA common request is to view a plot of the linear response o

Parametric Analysis 12-9Displaying results in ProbeUse Probe to display the capacitance calculated at the frequency of interest vs. the stepped parame

12-10 Parametric and Temperature Analysis6In the X value text box, type 10K.7Click Next>. The wizard displays the gain trace for the first run to t

Temperature Analysis 12-11Temperature AnalysisMinimum Requirements to Run a Temperature AnalysisMinimum circuit design requirementsNone.Minimum progra

12-12 Parametric and Temperature Analysisare recomputed based upon the CRES model which has parameters TC1 and TC2 reflecting linear and quadratic tem

Monte Carlo and Sensitivity/Worst-Case Analyses13Chapter OverviewThis chapter describes how to set up Monte Carlo and sensitivity/worst-case analyses

Part OneSimulation PrimerPart One provides basic information about circuit simulation including examples of common analyses.Chapter 1,Things You Need

13-2 Monte Carlo and Sensitivity/Worst-Case AnalysesStatistical AnalysesMonte Carlo and sensitivity/worst-case are statistical analyses. This section

Statistical Analyses 13-3Output Control for Statistical AnalysesMonte Carlo and sensitivity/worst-case analyses can generate the following types of re

13-4 Monte Carlo and Sensitivity/Worst-Case AnalysesWaveform ReportsFor Monte Carlo analyses, there are four variations of the output which can be spe

Statistical Analyses 13-5MIN find the minimum value of each waveformRISE_EDGE find the first occurrence of the waveform crossing above a specified thr

13-6 Monte Carlo and Sensitivity/Worst-Case AnalysesTemperature Considerations in Statistical AnalysesThe statistical analyses perform multiple runs,

Monte Carlo Analysis 13-7Monte Carlo AnalysisThe Monte Carlo analysis computes the circuit response to changes in component values by randomly varying

13-8 Monte Carlo and Sensitivity/Worst-Case AnalysesPSpice A/D starts as usual by running all of the analyses enabled in the Analysis Setup dialog wit

Monte Carlo Analysis 13-9There is a trade-off in choosing the number of Monte Carlo runs. More runs provide better statistics, but take proportionally

13-10 Monte Carlo and Sensitivity/Worst-Case AnalysesTutorial: Monte Carlo Analysis of a Pressure SensorIn this tutorial, you will see how the perform

Monte Carlo Analysis 13-11• Place the analog ground using the AGND symbol.• To connect the symbols, use Wire from the Draw menu.• To move values and/o

Things You Need to Know1Chapter OverviewThis chapter introduces the purpose and function of the PSpice A/D circuit simulator. What is PSpice A/D? on p

13-12 Monte Carlo and Sensitivity/Worst-Case Analyses4Click Save Attr to accept the changes. 5Click Change Display.6In the What to Display frame, choo

Monte Carlo Analysis 13-13Using resistors with modelsTo explore the effects of manufacturing tolerances on the behavior of this circuit, you will set

13-14 Monte Carlo and Sensitivity/Worst-Case AnalysesSaving the schematicBefore editing the models for the Rbreak resistors, save the schematic.To sav

Monte Carlo Analysis 13-15names it <old model name>-X, which in this tutorial, is Rbreak-X. In the model editor, you can change this name to wha

13-16 Monte Carlo and Sensitivity/Worst-Case AnalysesTo have resistors R2 and R4 use the same tolerances as R11Select R2.2From the Edit menu, select M

Monte Carlo Analysis 13-17Setting up the analysesDefine and enable a DC analysis that sweeps the pressure value, and a Monte Carlo analysis that runs

13-18 Monte Carlo and Sensitivity/Worst-Case AnalysesTo verify that the DC sweep and Monte Carlo analyses are enabled1In the Analysis Setup dialog box

Monte Carlo Analysis 13-19Monte Carlo HistogramsA typical application of Monte Carlo analysis is predicting yields on production runs of a circuit. Pr

13-20 Monte Carlo and Sensitivity/Worst-Case AnalysesSetting up the analysisTo analyze our filter, we will set up both an AC analysis and a Monte Carl

Monte Carlo Analysis 13-21To run the simulation and load Probe with data1From the Analysis menu, select Simulate. When complete, Probe automatically s

1-2 Things You Need to KnowWhat is PSpice A/D?MicroSim PSpice A/D is a simulation program that models the behavior of a circuit containing any mix of

13-22 Monte Carlo and Sensitivity/Worst-Case Analyses3Click Save and then OK. The histogram for 1 dB bandwidth is shown in Figure 13-10.Figure 13-101

Monte Carlo Analysis 13-23The statistics for the histogram are displayed along the bottom of the display. The statistics show the number of Monte Carl

13-24 Monte Carlo and Sensitivity/Worst-Case AnalysesFigure 13-11Center Frequency Histogram

Worst-Case Analysis 13-25Worst-Case AnalysisThis section discusses the analog worst-case analysis feature of PSpice A/D. The information provided in t

13-26 Monte Carlo and Sensitivity/Worst-Case AnalysesWorst is user-defined as the highest (HI) or lowest (LO) possible collating function relative to

Worst-Case Analysis 13-27model parameter. If a .PROBE statement is included in the circuit file, then the results of the nominal and worst-case runs a

13-28 Monte Carlo and Sensitivity/Worst-Case AnalysesWorst-Case Analysis ExampleThe schematic shown in Figure 13-12 is for an amplifier circuit which

Worst-Case Analysis 13-29conditions under which worst-case analysis works well and those that can produce misleading results when output is not monoto

13-30 Monte Carlo and Sensitivity/Worst-Case Analysesmaximized and Rb1 is minimized. Checking their individual effects is not sufficient, even if the

Worst-Case Analysis 13-31Figure 13-15Correct Worst-Case ResultsFigure 13-16Incorrect Worst-Case ResultsOutput is monotonic within the tolerance range.

Analyses You Can Run with PSpice A/D 1-3Analyses You Can Run with PSpice A/DBasic AnalysesDC sweep & other DC calculationsThese DC analyses evalua

13-32 Monte Carlo and Sensitivity/Worst-Case AnalysesHints and Other Useful InformationVARY BOTH, VARY DEV, and VARY LOTWhen VARY BOTH is specified in

Worst-Case Analysis 13-33manually adjust the nominal model parameter values according to the results, then perform another analysis with VARY DEV spec

13-34 Monte Carlo and Sensitivity/Worst-Case AnalysesManual optimizationWorst-case analysis can be used to perform manual optimization with PSpice A/D

Worst-Case Analysis 13-35Using Monte Carlo analysis with YMAX is a good way to obtain a conservative guess at the maximum possible deviation from nomi

Digital Simulation14Chapter OverviewThis chapter describes how to set up a digital simulation analysis and includes the following sections:What Is Dig

14-2 Digital SimulationWhat Is Digital Simulation?Digital simulation is the analysis of logic and timing behavior of digital devices over time. PSpice

Concepts You Need to Understand 14-3Concepts You Need to UnderstandStatesWhen the circuit is in operation, digital nodes take on values or output stat

14-4 Digital SimulationStrengthsWhen a digital node is driven by more than one device, PSpice A/D must determine the correct level of the node. Each o

Defining a Digital Stimulus 14-5Defining a Digital StimulusA digital stimulus defines input to the digital portions of your circuit, playing a similar

14-6 Digital SimulationUsing Top-Level Interface PortsInterface ports have two uses. You can use them to define:• connections only• stimuli and connec

iv ContentsFiles Needed for Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11Files That Schematics Gener

1-4 Things You Need to KnowAC sweep and noiseThese AC analyses evaluate circuit performance in response to a small-signal alternating current source.

Defining a Digital Stimulus 14-7To start the Stimulus Editor with default stimuli for ALL top-level interface ports1In Schematics, place interface por

14-8 Digital SimulationUsing the DIGSTIM SymbolThe DIGSTIM stimulus symbol allows you to define a stimulus for a net or bus using the Stimulus Editor.

Defining a Digital Stimulus 14-95Enter values for the clock signal properties as described below.6From the File menu, select Save.To change clock prop

14-10 Digital SimulationTo add a transition1In the Stimulus Editor, from the Edit menu, select Add.2Click the digital stimulus you want to edit.3Drag

Defining a Digital Stimulus 14-11To delete a transition1Click the transition you want to delete.2If needed, press V+click to select additional transit

14-12 Digital SimulationTo introduce transitions (method 1)1In the Stimulus Editor, from the Edit menu, select Add.2In the digital value field on the

Defining a Digital Stimulus 14-138Click OK.9Repeat steps 4 through 8 for each transition.To set the default bus radix1From the Tools menu, select Opti

14-14 Digital SimulationAdding loopsSuppose you have a stimulus that looks like this:and you want to create a stimulus that consists of three consecut

Defining a Digital Stimulus 14-156In the document that appears, find the set of consecutive lines comprising the sequence that you want to repeat. Eac

14-16 Digital SimulationUsing the DIGCLOCK SymbolThe DIGCLOCK symbol is way to define a clock signal by defining the symbol’s attributes.To define a c

Analyses You Can Run with PSpice A/D 1-5Transient and FourierThese time-based analyses evaluate circuit performance in response to time-varying source

Defining a Digital Stimulus 14-17When placed, each symbol must be connected to the wire or bus of the corresponding radix. Generally, only the FORMAT,

14-18 Digital SimulationUsing the FILESTIM DeviceFILESTIM has a single pin for connection to the rest of the circuit. The digital stimulus specificati

Defining a Digital Stimulus 14-19The following steps set up the U2 stimulus so that the 74393 counter is cleared after 40 nsec have elapsed in a trans

14-20 Digital SimulationDefining Simulation TimeTo set up the transient analysis1In Schematics, from the Analysis menu, select Setup.2Click Transient.

Adjusting Simulation Parameters 14-21Selecting Propagation DelaysAll of PSpice A/D’s digital devices, including the primitives and library models, per

14-22 Digital SimulationInitializing Flip-FlopsTo initialize all flip-flops and latches1Select one of the three Flip-flop Initialization choices in th

Analyzing Results 14-23Analyzing ResultsMicroSim Probe is the waveform analyzer for PSpice A/D simulations. Probe allows you to observe and manipulate

14-24 Digital Simulation•You can also type trace expression directly into the Trace Expression text box. A typical set of entries might be:IN1 IN2 Q1

Analyzing Results 14-25To add a digital trace expression1In the Add Trace dialog box, make sure that the Digital check box is selected (✓).2Do one of

14-26 Digital SimulationAdding Buses to a Probe PlotA set of up to 32 signals can be evaluated and displayed as a bus even if the selected signals wer

1-6 Things You Need to KnowAdvanced Multi-Run AnalysesThe multi-run analyses—parametric, temperature, Monte Carlo, and sensitivity/worst-case—result i

Analyzing Results 14-27To add a bus expression1In the Add Trace dialog box, in the Functions and Macros list, select Digital Operators and Functions.2

14-28 Digital SimulationTracking Timing Violations and HazardsWhen there are problems with your design, such as setup/hold violations, pulse-width vio

Analyzing Results 14-29unrelated origins, therefore nothing in common) at the inputs to gate G1, PSpice A/D reports the occurrence as an AMBIGUITY CON

14-30 Digital Simulationhazard origin information along with the machine state through all digital devices. When a hazard propagates to a state-storag

Analyzing Results 14-31Table 14-4Simulation Condition Messages—Timing ViolationsMessage TypeSeverity LevelMeaningSETUP WARNING Minimum time required f

14-32 Digital SimulationTable 14-5Simulation Condition Messages—HazardsMessage TypeSeverity LevelMeaningAMBIGUITYCONVERGENCEWARNING Convergence of con

Analyzing Results 14-33Output control optionsSeveral control options in the Analysis Setup Options dialog box are available for managing the generatio

Mixed Analog/Digital Simulation15Chapter OverviewThis chapter describes how PSpice A/D runs mixed analog/digital simulations and includes the followin

15-2 Mixed Analog/Digital Simulationnetlist. The netlist presents a flat view of the circuit (no hierarchy). Furthermore, PSpice A/D extracts the defi

Interface Subcircuit Selection by PSpice A/D 15-3Interface Subcircuit Selection by PSpice A/DAtoD and DtoA interface subcircuits handle the translatio

Analyses You Can Run with PSpice A/D 1-7Monte Carlo and sensitivity/worst-caseMonte Carlo and sensitivity/worst-case analyses are statistical. PSpice

15-4 Mixed Analog/Digital SimulationIn the HC/HCT series, we provide two different DtoA models: the simple model and the elaborate model. The simple m

Interface Subcircuit Selection by PSpice A/D 15-5it provides a more accurate, less optimistic answer. However, this behavior may not be appropriate wh

15-6 Mixed Analog/Digital SimulationSetting the Default A/D InterfaceFor mixed-signal simulation, you can select the AtoD and DtoA interface level cir

Specifying Digital Power Supplies 15-7Specifying Digital Power SuppliesDigital power supplies are used to power interface subcircuits that are automat

15-8 Mixed Analog/Digital Simulationwith all primitives appropriately connected to the power supply nodes.Table 15-2 summarizes the default node names

Specifying Digital Power Supplies 15-9listed in Table 15-3 in your schematic and redefining the digital power supply nodes.The attributes relevant to

15-10 Mixed Analog/Digital Simulation3Reset the power supply power and ground voltages as required. 4For any digital part instance that use the power

Specifying Digital Power Supplies 15-11Creating a secondary CD4000, TTL, or ECL power supplyCircuits using CD4000, TTL, or ECL parts may require power

15-12 Mixed Analog/Digital SimulationInterface Generation and Node NamesThe majority of the interface generation process involves PSpice A/D determini

Interface Generation and Node Names 15-13node, 2$DtoA, to connect the output of U1 to the digital input of the DtoA interface.The interface subcircuit

1-8 Things You Need to KnowUsing PSpice A/D with Other MicroSim ProgramsFigure 1-1 illustrates the design flow for simulating a circuit and the progra

15-14 Mixed Analog/Digital Simulationresistance) subcircuit parameter values are also obtained from the same I/O model.After the interface subcircuit

Digital Worst-Case Timing Analysis16Chapter OverviewThis chapter deals with worst-case timing analysis and includes the following sections:Digital Wo

16-2 Digital Worst-Case Timing AnalysisDigital Worst-Case TimingManufacturers of electronic components generally specify component parameters (such as

Starting Worst-Case Timing Analysis 16-3Starting Worst-Case Timing Analysis1In the Analysis Setup dialog box, click on the Digital Setup button. Set T

16-4 Digital Worst-Case Timing Analysisthe duration of the timing ambiguity result that represents a primitive’s output change.For example, consider t

Propagation of Timing Ambiguity 16-5Propagation of Timing AmbiguityAs signals propagate through the circuit, ambiguity is contributed by each primitiv

16-6 Digital Worst-Case Timing AnalysisIdentification of Timing HazardsTiming hazard is the term applied to situations in which the response of a devi

Critical Hazard 16-7This output (0-R-0) should be interpreted as a possible single pulse, no longer than the duration of the R level. The actual devic

16-8 Digital Worst-Case Timing AnalysisCumulative Ambiguity HazardIn worst-case mode, simple signal propagation through the network will result in a b

Cumulative Ambiguity Hazard 16-9Another cause of cumulative ambiguity hazard involves circuits with asynchronous feedback. The simulation of such circ

Using PSpice A/D with Other MicroSim Programs 1-9Using Schematics to Prepare for Simulation Schematics is a design entry program you need to prepare y

16-10 Digital Worst-Case Timing AnalysisReconvergence HazardThe simulator recognizes situations where signals having a common origin reconverge on the

Reconvergence Hazard 16-11In the event that discounting the common ambiguity does not preclude the X being latched (or, in the case of simple gates, a

16-12 Digital Worst-Case Timing AnalysisGlitch Suppression Due to Inertial DelaySignal propagation through digital primitives is performed by the simu

Methodology 16-13amount of overlap is less than the inertial delay of the device, the prediction of a glitch is also suppressed by the simulator (see

16-14 Digital Worst-Case Timing AnalysisDigital worst-case timing simulation does not yield such results without an applied stimulus; it is not a stat

Methodology 16-15For example, in the case of a convergence or reconvergence hazard, look for conflicting rise/fall inputs. In the case of cumulative a

Part FourViewing ResultsPart Four describes the ways to view simulation results.Chapter 17,Analyzing Waveforms in Probe, describes how to perform grap

Analyzing Waveformsin Probe17Chapter OverviewThis chapter describes how to use Probe to perform graphical waveform analysis of simulation results. Thi

17-2 Analyzing Waveforms in ProbeOverview of ProbeMicroSim Probe is the waveform analyzer for PSpice A/D simulations. In Probe, you can visually analy

Overview of Probe 17-3Elements of a Probe PlotA single Probe plot consists of the analog (lower) area and the digital (upper) area.You can display mul

1-10 Things You Need to KnowWhat is the Parts Utility? The Parts utility is a model extractor that generates model definitions for PSpice A/D to use d

17-4 Analyzing Waveforms in ProbeElements of a Plot WindowA plot window is a separately managed waveform display area. A plot window can include multi

Overview of Probe 17-5Managing Multiple Plot WindowsAny number of plot windows can be opened. Each plot window is an independent window.The same Probe

17-6 Analyzing Waveforms in ProbeSetting Up ProbeConfiguring Probe ColorsYou can configure Probe display and print colors in:• the configuration file,

Setting Up Probe 17-74If you added or deleted trace number entries, set NUMTRACECOLORS=n to the new number of traces (1≤n≤12). This item represents th

17-8 Analyzing Waveforms in ProbeConfiguring trace color schemesIn the Probe Options dialog box, you can set options for how the available colors and

Setting Up Probe 17-9Customizing the Probe Command LineCommand files, .prb files, and options can be specified in the Probe command line. Probe recogn

17-10 Analyzing Waveforms in ProbeRunning ProbeStarting ProbeIf you are using Schematics, you can automatically start Probe after a simulation is run,

Running Probe 17-115From the Analysis menu, select Simulate to start the simulation. Probe starts automatically and displays one window in monitor mod

17-12 Analyzing Waveforms in ProbeOther Ways to Run ProbeStarting Probe during a simulationOnce a simulation is in progress, you can monitor the resul

Running Probe 17-13Interacting with Probe while in monitor modeAll of the Probe functionality is available when in monitor mode. However, functions th

Files Needed for Simulation 1-11Files Needed for SimulationTo simulate your design, PSpice A/D needs to know about:• the parts in your circuit and how

17-14 Analyzing Waveforms in Probe•During or after simulation, with Probe running, to automatically display traces in the active plot window.You can a

Running Probe 17-154Right-click to quit placing markers.5If you have not simulated the circuit yet, from the Analysis menu, select Simulate.To control

17-16 Analyzing Waveforms in ProbeLimiting file size using markersOne reason that Probe data files are large is that, by default, PSpice A/D stores al

Running Probe 17-17Limiting file size by excluding internal subcircuit dataBy default, PSpice A/D writes data to the Probe file for all internal nodes

17-18 Analyzing Waveforms in ProbeUsing Simulation Data from Multiple FilesYou can load simulation data from multiple files into the same Probe plot i

Running Probe 17-194In the Show Results In frame, choose one of the following options:5Click OK.Appending data filesYou can manually load data sets on

17-20 Analyzing Waveforms in ProbeAdding traces from specific loaded data filesIf two or more data files have identical simulation output variables, t

Running Probe 17-21Figure 17-4Section Information Message BoxSaving Simulation Results in ASCII FormatThe default Probe data file format is binary. Ho

17-22 Analyzing Waveforms in ProbeAnalog ExampleIn this section, basic techniques for operating Probe are demonstrated using the analog circuit Exampl

Analog Example 17-23PSpice A/D generates a binary Probe data file containing the results of the simulation. The Probe screen displays with the data fi

1-12 Things You Need to KnowNetlist fileThe netlist file contains a list of device names, values, and how they are connected with other devices. The n

17-24 Analyzing Waveforms in ProbeDisplaying voltages on nets and currents into pinsHaving selected an analysis, voltages on nets and currents into de

Mixed Analog/Digital Tutorial 17-25Mixed Analog/Digital TutorialIn this tutorial, you will use PSpice A/D to simulate a simple, mixed analog/digital c

17-26 Analyzing Waveforms in ProbeAbout the Oscillator CircuitThe circuit you will simulate and analyze is a mixed analog/digital oscillator using Sch

Mixed Analog/Digital Tutorial 17-27Running the SimulationTo run the simulation1From the Analysis menu, select Simulate.Because the oscillator circuit

17-28 Analyzing Waveforms in ProbeTo view traces for V(3), RESET, and OUT1From the Trace menu, select Add. 2In the Simulation Output Variables list, c

Mixed Analog/Digital Tutorial 17-29Figure 17-10Mixed Analog/Digital Oscillator Results

17-30 Analyzing Waveforms in ProbeUser Interface FeaturesProbe offers a number of direct manipulation techniques and shortcuts to analyze the waveform

User Interface Features 17-31To zoom in the analog area using the mouse1Drag the mouse to make a selection rectangle as shown below. 2From the View me

17-32 Analyzing Waveforms in ProbeScrolling TracesBy default, when a plot is zoomed or when a digital plot contains more traces than can be displayed

User Interface Features 17-33Sizing Digital Plots Sizing bars can be used to change the digital plot size instead of using Digital Size from the Plot

Files Needed for Simulation 1-13Before starting simulation, PSpice A/D needs to read other files that contain simulation information for your circuit.

17-34 Analyzing Waveforms in ProbeTo set the digital plot size using menu options1Display at least one digital trace in the plot for which you want to

User Interface Features 17-35Moving and Copying Trace Names and ExpressionsTrace names and expressions can be selected and moved or copied, either wit

17-36 Analyzing Waveforms in ProbeCopying and Moving LabelsLabels can be selected and moved or copied, either within the same plot window or to anothe

User Interface Features 17-37To export the data points to other Windows 95 or NT programs1Select one or more (V+click) traces. Selected traces are hig

17-38 Analyzing Waveforms in ProbeTo move cursors along a trace using menu commands1From the Tools menu, point to Cursor, then select Peak, Trough, Sl

User Interface Features 17-39To move cursors along a trace using the keyboard1Use key combinations as described in Table 17-3. Example: Using cursors

17-40 Analyzing Waveforms in ProbeCursor 1 is positioned on the first trough (dip) of the V(1) waveform. Cursor 2 is positioned on the second peak of

Tracking Digital Simulation Messages 17-41Tracking Digital Simulation MessagesProbe provides an interactive message facility that automatically associ

17-42 Analyzing Waveforms in ProbeThe Simulation Message Summary dialog boxThe Simulation Message Summary dialog box lists message header information.

Tracking Digital Simulation Messages 17-43Message Tracking from the WaveformTrace segments with associated diagnostics are displayed in the foreground

Contents vPart Two Design EntryPreparing a Schematic for SimulationChapter 3Chapter Overview . . . . . . . . . . . . . . . . . . .

1-14 Things You Need to KnowStimulus fileA stimulus file contains time-based definitions for analog and/or digital input waveforms. You can create a s

17-44 Analyzing Waveforms in ProbeProbe Trace ExpressionsTraces are referred to by Probe output variable names. Probe output variables are similar to

Probe Trace Expressions 17-45Basic Output Variable FormThis form is representative of those used for specifying some PSpice A/D analyses.<output>

17-46 Analyzing Waveforms in ProbeOutput Variable Form for Device TerminalsThis form can only be specified in Probe. The primary difference between th

Probe Trace Expressions 17-47Table 17-4Probe Output Variable FormatsFormat MeaningVoltage VariablesV[ac](< +analog net > [,< -analog net >

17-48 Analyzing Waveforms in Probe*. See Table 17-9 on page 17-52 for a complete list of noise types by device type. For information about noise outpu

Probe Trace Expressions 17-49Table 17-5Examples of Probe Output Variable FormatsA Basic FormAn alias equivalentMeaningV(NET3,NET2) (same) voltage betw

17-50 Analyzing Waveforms in Probe*. The pin name for two-terminal devices is either 1 or 2.**. The controlling inputs for these devices are not consi

Probe Trace Expressions 17-51Table 17-8Terminal IDs by Three & Four-Terminal Device TypeThree & Four-Terminal Device TypeDevice Type LetterTer

17-52 Analyzing Waveforms in ProbeTable 17-9Noise Types by Device TypeDevice TypeNoise Types*MeaningB (GaAsFET) FIDRDRGRSSIDTOTflicker noisethermal no

Probe Trace Expressions 17-53*. These variables report the contribution of the specified device’s noise to the total output noise in units of V2/Hz. T

Files That PSpice A/D Generates 1-15Files That PSpice A/D GeneratesFigure 1-4Data Files That PSpice A/D CreatesAfter first reading the circuit file, n

17-54 Analyzing Waveforms in ProbeAnalog Trace ExpressionsTrace expression aliasesAnalog trace expressions in Probe vary from the output variables use

Probe Trace Expressions 17-55NoteFor AC analysis, Probe uses complex arithmetic to evaluate expressions. If the result of the expression is complex, t

17-56 Analyzing Waveforms in ProbeRules for numeric values suffixesExplicit numeric values are entered in the same form as PSpice A/D (by means of sym

Probe Trace Expressions 17-57Digital Trace ExpressionsDigital output variables in Probe vary from those used in PSpice A/D analyses as follows:• Digi

17-58 Analyzing Waveforms in ProbeTable 17-12 presents the operators available for digital signal and bus expressions listed in order of precedence (h

Probe Trace Expressions 17-59You can use signal constants in signal expressions. Specify them as shown in Table 17-13.You can use bus constants in bus

Viewing Results on the Schematic18Chapter OverviewThis chapter describes how to view bias point information directly on your schematic after running a

18-2 Viewing Results on the SchematicViewing Bias Point Voltagesand CurrentsAfter simulating, you can display bias point information on your schematic

Viewing Bias Point Voltages and Currents 18-3• A given voltage or current source can have a different DC value and initial transient value at TIME=0.

18-4 Viewing Results on the SchematicShowing Voltages By default, voltage display is initially enabled for all nets in your schematic. This means bias

1-16 Things You Need to KnowPSpice output fileThe PSpice output file is an ASCII text file that contains:• the netlist representation of the circuit,

Viewing Bias Point Voltages and Currents 18-5To view a subset of the voltages that are already displayed1From the Edit menu, select Select All.2From t

18-6 Viewing Results on the SchematicShowing CurrentsBy default, current display is initially disabled for all device pins in your schematic. When you

Viewing Bias Point Voltages and Currents 18-7Changing the Precision of Displayed DataBy default, Schematics displays voltage and current values with f

18-8 Viewing Results on the SchematicNoteSchematics remembers the position of voltage labels, but not current labels. This means if you close (after h

Viewing Bias Point Voltages and Currents 18-9Changing Display ColorsYou can change the appearance of the voltage and current labels using Display Pref

18-10 Viewing Results on the SchematicIf you want obsolete voltage and current labels to change appearanceWhen you change your schematic, the voltage

Other Ways to View Bias Point Values 18-11Other Ways to View Bias Point ValuesFor the analog portion of your circuit, Schematics provides two special

18-12 Viewing Results on the Schematic2Run the simulation.When the simulation completes, Schematics displays the bias point current next to the IPROBE

Other Output Options19Chapter OverviewThis chapter describes how to output results in addition to those normally written to the Probe data file or PSp

19-2 Other Output OptionsViewing Analog Results in the PSpice WindowSchematics provides a special WATCH1 symbol that lets you monitor voltage values f

Simulation Examples2Chapter OverviewThe examples in this chapter provide an introduction to the methods and tools for creating circuit designs, runnin

Writing Additional Results to the PSpice Output File 19-3Writing Additional Results to the PSpice Output FileSchematics provides special symbols that

19-4 Other Output Options5If you selected the AC analysis type, enable an output format:aClick the attribute name for one of the following output form

Writing Additional Results to the PSpice Output File 19-54In the Value text box, type any non-blank value such as Y, YES, or 1.5If you selected the AC

19-6 Other Output OptionsCreating Test Vector FilesSchematics provides a special VECTOR symbol that lets you save digital simulation results to a vect

Setting Initial StateAAppendix OverviewThis appendix includes the following sections:Save and Load Bias Point on page A-2Setpoints on page A-4Setting

A-2 Setting Initial StateSave and Load Bias PointSave Bias Point and Load Bias Point are used to save and restore bias point calculations in successiv

Save and Load Bias Point A-3Load Bias PointLoad bias point is a simulation control function that allows you to set the bias point as an initial condit

A-4 Setting Initial StateSetpointsPseudocomponents that specify initial conditions are called setpoints. These apply to the analog portion of your cir

Setpoints A-5Unlike the IC pseudocomponents, NODESET provides only an initial guess for some net voltages. It does not clamp those nodes to the specif

A-6 Setting Initial StateSetting Initial ConditionsThe IC attribute allows initial conditions to be set on capacitors and inductors. These conditions

2-2 Simulation ExamplesExample Circuit CreationThis section describes how to use MicroSim Schematics to create the simple diode clipper circuit shown

Convergence and “Time Step Too Small Errors”BAppendix OverviewThis appendix discusses common errors and convergence problems in PSpice.Introduction on

B-2 Convergence and “Time Step Too Small Errors”IntroductionIn order to calculate the bias point, DC sweep and transient analysis for analog devices P

Introduction B-3Each of these can be taken in order. One must keep in mind that PSpice’s algorithms are used in computer hardware that has finite prec

B-4 Convergence and “Time Step Too Small Errors”Are the Equations Continuous?The device equations built into PSpice are continuous. The functions avai

Introduction B-5Is the Initial Approximation Close Enough?It seems like a Catch-22: Newton-Raphson is guaranteed to converge only if the analysis is s

B-6 Convergence and “Time Step Too Small Errors”STEPGMINAn alterative algorithm is GMIN stepping. This is not obtained by default, and is enabled by s

Bias Point and DC Sweep B-7Bias Point and DC SweepPower supply steppingAs previously discussed, PSpice uses a proprietary algorithm which finds a cont

B-8 Convergence and “Time Step Too Small Errors”No leakage resistanceA third consideration is to avoid situations which could have an ideal current so

Bias Point and DC Sweep B-9Behavioral Modeling ExpressionsRange limitsVoltages and currents in PSpice are limited to the range +/- 1e10. Care must be

B-10 Convergence and “Time Step Too Small Errors”Example: A first approximation to an opamp that has an open loop gain of 100,000 is:VOPAMP 3, 5 VALUE

Example Circuit Creation 2-34Move the pointer to the correct position on the schematic (see Figure 2-1) and click to place the first source.5Move the

Transient Analysis B-11Skipping the Bias PointThe SKIPBP option for the transient analysis skips the bias point calculation. In this case the transien

B-12 Convergence and “Time Step Too Small Errors”Failure at the First Time StepIf the transient analysis fails at the first time point then usually th

Transient Analysis B-13Parasitic CapacitancesIt is important that switching times be nonzero. This is assured if devices have parasitic capacitances.

B-14 Convergence and “Time Step Too Small Errors”The parallel resistor gives a good model for eddy current loss and limits the bandwidth of the induct

Diagnostics B-15DiagnosticsIf PSpice encounters a convergence problem it inserts into the output file a message that looks like the following.The mess

B-16 Convergence and “Time Step Too Small Errors”The Last node voltages tried... trailer shows the voltages tried at the last Newton-Raphson iteration

IndexAABMABM part templates, 6-6abm.slb, 6-3basic controlled sources, 6-46cautions and recommendations for simulation, 6-40control system parts, 6-7cu

Index-2IGBT, 4-12, 8-9, 17-51inductors, 8-8integrators and differentiators (ABM), 6-7, 6-14JFET, 4-12, 8-9, 17-51, 17-52Laplace transform (ABM), 6-8,

Index-3approximations, B-5behavioral modeling expressions, B-9bias point, B-7bipolar transistors, B-14continuous equations, B-4DC sweep, B-7derivative

Index-4DRVL (I/O model parameter), 15-13DRVL (I/O model), 7-18, 7-22DRVZ (I/O model), 7-18DtoA interface, see mixed analog/digital circuitsdynamic ran

2-4 Simulation ExamplesTo connect the components1From the Draw menu, select Wire to enter wiring mode. The cursor changes to a pencil.2Click the conne

Index-5IF_IN interface port symbol, 3-26, 14-5, 14-6IGBT, 4-12, 8-9, 17-51imaginary part, 17-49include files, 1-12configuring, 1-14, 4-41with model de

Index-6schematic editor, 4-33symbol editor, 4-31model libraries, 1-12, 4-4adding to the configuration, 4-44analog list of, 3-29and duplicate model nam

Index-7DIGMNTYMX, 16-3DIGMNTYSCALE, 7-12DIGOVRDRV, 7-23DIGTYMXSCALE, 7-12NOOUTMSG, 14-33NOPRBMSG, 14-33RELTOL, 6-45origin, symbol, 5-16OUTLD (I/O mode

Index-8multiple Y axes, 12-6, 17-27output variables, 17-44, 17-57for noise, 10-12, 17-52performance analysis, 2-30, 12-3placing a cursor on a trace, 2

Index-9DC sweep, 9-5for multiple analysis types, 3-25loops (digital), 14-14signal transitions (digital), 14-9transient (analog/mixed-signal), 11-3tran

Index-10VIEWPOINT (bias point voltage display), 18-11VPULSE (transient stimulus), 3-23VPWL (transient stimulus), 3-23VPWL_F_N_TIMES (transient stimulu

Index-11switching times (TSW), 7-11transport delay, 7-16unspecified timing constraints, 7-13timing violations and hazardsconvergence, 14-32cumulative

Index-12waveform reports, 13-4with temperature analysis, 13-6Zzoom regions, Probe, 17-30

Example Circuit Creation 2-54Continue naming devices until all circuit devices are named as in Figure 2-1 on page 2-2.To change the attribute values o

2-6 Simulation ExamplesBias Point AnalysisRunning PSpice A/DWhen you perform a simulation, PSpice A/D generates an output file (for this example, clip

Bias Point Analysis 2-7Using the Bias Information DisplayYou can display bias information on your schematic, including voltages for all nets and curre

vi ContentsMissing Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32Check for this . . . .

2-8 Simulation ExamplesTo display bias current through V1, R2, and D11In Schematics, make the clipper.sch window active.2On the Simulation toolbar, cl

Bias Point Analysis 2-9Using the Simulation Output File The simulation output file acts as an audit trail of the simulation. This file optionally echo

2-10 Simulation ExamplesNote that the current through VIN is negative. By convention, PSpice A/D measures the current through a two terminal device in

DC Sweep Analysis 2-112In the Analysis Setup dialog box, click the DC Sweep button.3Set up the DC Sweep dialog box as shown in Figure 2-6.NoteThe defa

2-12 Simulation Examples2Click to place a marker on net Out (Figure 2-8).Figure 2-8Clipper Circuit with Voltage Marker on Net Out3Right-click to cance

DC Sweep Analysis 2-13To place cursors on V(In) and V(Mid)1In Probe, from the Tools menu, point to Cursor, then select Display.Two cursors appear for

2-14 Simulation Examples3Place the first cursor on the V(In) waveform:aClick the portion of the V(In) trace in the proximity of 4 volts on the x-axis.

DC Sweep Analysis 2-15Figure 2-12 shows the Probe window when both cursors are placed.Figure 2-12Voltage Difference at V(In) = 4 VoltsTo delete all of

2-16 Simulation ExamplesTransient AnalysisThis example shows how to run a transient analysis on the clipper circuit. This requires adding a time-domai

Transient Analysis 2-176From the Edit menu, select Paste.7Place the ground symbol under the VSTIM symbol as shown in Figure 2-13.8From the View menu,

Contents viiEntering data sheet information . . . . . . . . . . . . . . . . . . . . . 4-24Extracting model parameters . . . .

2-18 Simulation Examples15Click OK.16From the File menu, select Save to save the stimulus information.17From the File menu, select Exit.To set up and

Transient Analysis 2-193Click OK to display the traces.4Place the symbols shown in the trace legend on the traces themselves as shown in Figure 2-16:a

2-20 Simulation ExamplesAC Sweep AnalysisThe AC sweep analysis in PSpice A/D is a linear (or small signal) frequency domain analysis that can be used

AC Sweep Analysis 2-214In the Replace Part dialog box, type VAC.5Select ( ✓) the Keep Attribute Values check box.6Click OK. The input voltage source c

2-22 Simulation ExamplesAC Sweep Analysis ResultsProbe displays the dB magnitude (20log10) of the voltage at the marked nets, Out and Mid, as shown in

AC Sweep Analysis 2-236From the Edit menu, select Cut.7From the Plot menu, select Add Y Axis.8From the Edit menu, select Paste. The Bode plot appears

2-24 Simulation ExamplesParametric AnalysisThis example shows the effect of varying input resistance on the bandwidth and gain of the clipper circuit

Parametric Analysis 2-25Setting Up and Running the Parametric AnalysisTo change the value of R1 to the expression {Rval}1In Schematics, open clippera.

2-26 Simulation ExamplesTo set up and run a parametric analysis to step the value of R1 using Rval1From the Analysis menu, select Setup.2In the Analys

Parametric Analysis 2-27Analyzing Waveform Families in ProbeThere are 21 analysis runs, each with a different value of R1. When Probe starts, it displ

viii ContentsUsing the Symbol Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6How to Start the Symbol

2-28 Simulation ExamplesNoteThe difference in gain is apparent. You can also plot the difference of the waveforms for runs 21 and 1 and then use the s

Parametric Analysis 2-29Finding Out More about Parametric AnalysisTo find out more about this...See this...Parametric analysisParametric Analysis on p

2-30 Simulation ExamplesProbe Performance AnalysisPerformance analysis is an advanced feature in Probe that you can use to compare the characteristics

Probe Performance Analysis 2-319Click Next> or Finish. Probe displays a plot of the 3 dB bandwidth vs. Rval.10Change the x-axis to log scale.aFrom

2-32 Simulation ExamplesFinding Out More about Performance AnalysisTo find out more about this...See this...How to use performance analysisExample: RL

Part TwoDesign EntryPart Two provides information about how to enter circuit designs that you want to simulate in MicroSim Schematics.Chapter 3,Prepar

Preparing a Schematic for Simulation3Chapter OverviewThis chapter provides introductory information to help you enter circuit designs that simulate pr

3-2 Preparing a Schematic for SimulationChecklist for Simulation SetupThis section is provided so you can quickly step through what you need to do to

Checklist for Simulation Setup 3-3For more information on this step...See this... To find out this...✔Place markers.Using Schematic Markers to Add Tra

3-4 Preparing a Schematic for SimulationAdvanced Design Entry and Simulation Setup StepsWhen Netlisting Fails or the Simulation Does Not StartIf you h

Contents ixIntegrator and Differentiator . . . . . . . . . . . . . . . . . . . . . . . . 6-14Table Look-Up Parts . . .

Checklist for Simulation Setup 3-5To get online information about an error or warning shown in the Message Viewer1Select the error or warning message.

3-6 Preparing a Schematic for SimulationThings to check in your system configurationMake sure that... To find out more, see this...✔Path to the PSpice

Using Parts That You Can Simulate 3-7Using Parts That You Can SimulateThe MicroSim libraries supply numerous parts designed for simulation. These incl

3-8 Preparing a Schematic for SimulationVendor-Supplied PartsThe MicroSim libraries provide an extensive selection of manufacturers’ analog and digita

Using Parts That You Can Simulate 3-9Notice the following:• There is a generic OP-27 symbol provided by MicroSim, the OP-27/AD from Analog Devices, In

3-10 Preparing a Schematic for SimulationTo find parts using the online Library List1From the Help menu in Schematics, PSpice A/D, or the Parts utilit

Using Parts That You Can Simulate 3-11Passive PartsThe MicroSim libraries supply several basic parts based on the passive device models built-in to PS

3-12 Preparing a Schematic for SimulationBreakout PartsThe MicroSim libraries supply passive and semiconductor parts with default model definitions th

Using Parts That You Can Simulate 3-13Behavioral PartsBehavioral parts allow you to define how a block of circuitry should work without having to defi

3-14 Preparing a Schematic for SimulationUsing Global Parameters and Expressions for ValuesIn addition to literal values, you can use global parameter